The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a vertical transistor which includes a bottom source/drain structure that is in close proximity to the semiconductor fin and has increased volume, as well as a method of forming such a structure.
Conventional vertical transistors are devices where the source-drain current flows in a direction normal to the substrate surface. In such devices, a vertical semiconductor pillar (or fin) defines the channel with the source and drain located at opposing ends of the semiconductor pillar. Vertical transistors are an attractive option for technology scaling for 5 nm and beyond.
In such vertical transistors, the formation of the bottom source/drain structure by epitaxy and subsequent formation of extensions and junctions are challenging. There is a desire to provide a closer proximity for bottom source/drain epitaxy. Additionally, the volume of the bottom source/drawn structure in typical prior art vertical transistors is small leading to access resistance far above process assumptions desired. Attempts to form closer proximity and to increase the proximity with anisotropic etching has shown to be very hard to control and may often lead to the collapsing of the semiconductor fins. Also, the volume gain using such processing is rather small. There is thus a need for providing vertical transistors in which the bottom source/drain structure can be fabricated in closer proximity to the semiconductor fins without fin collapsing and with increased volume.